Publications
Conference and journal papers, book chapters, doctoral theses, and patents from the group. Links go to the publisher's version (DOI) and, where we have one, a PDF.
2026
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Can Fine-Grain Multi-threading Subsume VLIW?
LCTES 2026 · Proceedings of the 27th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 129–141
2024
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Statically Controlled Synchronized Lane Architectures
Ph.D. thesis · Michigan Technological University
2023
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Facilitating the Bootstrapping of a New ISA
LCTES 2023 · Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, pp. 2–12
2021
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Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache
ACM TACO · ACM Transactions on Architecture and Code Optimization, vol. 18, no. 3, pp. 1–22
2020
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Dynamic Dependency Collapsing
Ph.D. thesis · Michigan Technological University
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Demand-Driven Execution Using Future Gated Single Assignment Form
Ph.D. thesis · Michigan Technological University
2019
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Improving Energy Efficiency by Memoizing Data Access Information
ISLPED 2019 · IEEE/ACM International Symposium on Low Power Electronics and Design, pp. 1–6
2018
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Dynamic Memory Dependence Predication
ISCA 2018 · Proceedings of the 45th Annual International Symposium on Computer Architecture, Los Angeles, pp. 235–246
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A Two-Phase Recovery Mechanism
ICS 2018 · Proceedings of the 2018 International Conference on Supercomputing, Beijing, pp. 107–117
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Decoupling Address Generation from Loads and Stores to Improve Data Access Energy Efficiency
LCTES 2018 · Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, Philadelphia, pp. 65–75
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Mitigating the Effect of Misspeculations in Superscalar Processors
Ph.D. thesis · Michigan Technological University
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Demand Driven Execution Pipeline
Technical report · Michigan Technological University
2015
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LaZy Superscalar
ISCA 2015 · Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, pp. 260–271
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Mower: A New Design for Non-blocking Misprediction Recovery
ICS 2015 · Proceedings of the 29th ACM International Conference on Supercomputing, Newport Beach, pp. 285–294
2014
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Verifying Micro-architecture Simulators Using Event Traces
ICS 2014 · Proceedings of the 28th ACM International Conference on Supercomputing, Munich, pp. 323–332
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Single Assignment Compiler, Single Assignment Architecture: Future Gated Single Assignment Form; Static Single Assignment with Congruence Classes
CGO 2014 · Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, Orlando, pp. 196–207
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Mining and Verification of Temporal Events with Applications in Computer Micro-Architecture Research
Ph.D. thesis · Michigan Technological University (co-advised with Nilufer Önder)
2013
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A First-Order Logic Based Framework for Verifying Simulations
AAAI 2013 · Proceedings of the 27th AAAI Conference on Artificial Intelligence
2012
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Future Value Based Single Assignment Program Representations and Optimizations
Ph.D. thesis · Michigan Technological University
2011
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Discovering Patterns for Architecture Simulation by Using Sequence Mining
Book chapter · In Pattern Discovery Using Sequence Data Mining: Applications and Studies (P. Kumar, P. Radha Krishna, S. Bapi Raju, eds.), IGI Global
2010
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Unrestricted Code Motion: A Program Representation and Transformation Algorithms Based on Future Values
CC 2010 · Compiler Construction, LNCS 6011, Springer, Paphos, pp. 26–45
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Methods and Systems for Ordering Instructions Using Future Values
U.S. Patent 7,747,993 · Filed Dec 30, 2004; issued Jun 29, 2010
2009
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Fine-Grain State Processors
Ph.D. thesis · Michigan Technological University
2008
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Improving Single-Thread Performance with Fine-Grain State Maintenance
CF 2008 · Proceedings of the 5th ACM Conference on Computing Frontiers, Ischia, pp. 251–260
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ADL++: Object-Oriented Specification of Complicated Instruction Sets and Microarchitectures
Book chapter · In Processor Description Languages (P. Mishra and N. Dutt, eds.), Morgan Kaufmann, chapter 10, pp. 247–274
2006
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Feedback-Directed Memory Disambiguation Through Store Distance Analysis
ICS 2006 · Proceedings of the 20th ACM International Conference on Supercomputing, Cairns, pp. 278–287
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Path-Based Reuse Distance Analysis
CC 2006 · Compiler Construction, LNCS 3923, Springer, Vienna, pp. 32–46
2005
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Instruction Based Memory Distance Analysis and Its Application to Optimization
PACT 2005 · 14th International Conference on Parallel Architectures and Compilation Techniques, St. Louis, pp. 27–37
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Fast Branch Misprediction Recovery in Out-of-Order Superscalar Processors
ICS 2005 · Proceedings of the 19th ACM International Conference on Supercomputing, Boston, pp. 41–50
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A Case for a Working-Set-Based Memory Hierarchy
CF 2005 · Proceedings of the 2nd ACM Conference on Computing Frontiers, Ischia, pp. 252–261
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Specification of Intel IA-32 Using an Architecture Description Language
Book chapter · In Architecture Description Languages, IFIP vol. 176, Springer, pp. 151–166
2004
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Reuse-Distance-Based Miss-Rate Prediction on a Per Instruction Basis
MSP 2004 · Proceedings of the 2004 ACM Workshop on Memory System Performance, Washington, DC, pp. 60–68
2002
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Cost Effective Memory Dependence Prediction Using Speculation Levels and Color Sets
PACT 2002 · International Conference on Parallel Architectures and Compilation Techniques, Charlottesville, pp. 232–241
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Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC 2002 · Compiler Construction, LNCS 2304, Springer, Grenoble, pp. 85–100
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Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing
JILP · Journal of Instruction-Level Parallelism, vol. 4
2001
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Load and Store Reuse Using Register File Contents
ICS 2001 · Proceedings of the 15th ACM International Conference on Supercomputing, Naples, pp. 289–302
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Instruction Wake-Up in Wide Issue Superscalars
Euro-Par 2001 · Euro-Par 2001 Parallel Processing, LNCS 2150, Springer, Manchester, pp. 418–427
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Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches
Book chapter · In Interaction between Compilers and Computer Architectures (G. Lee and P.-C. Yew, eds.), Kluwer Academic Publishers, pp. 69–88
1999
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Caching and Predicting Branch Sequences for Improved Fetch Effectiveness
PACT 1999 · International Conference on Parallel Architectures and Compilation Techniques, Newport Beach
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Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing
MICRO-32 · Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, Haifa, pp. 170–176
1998
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Superscalar Execution with Dynamic Data Forwarding
PACT 1998 · International Conference on Parallel Architectures and Compilation Techniques, Paris, pp. 130–135
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Automatic Generation of Microarchitecture Simulators
ICCL 1998 · IEEE International Conference on Computer Languages, Chicago, pp. 80–89
1995
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SINAN: A Forwarding Multithreaded Architecture
HiPC 1995 · International Conference on High Performance Computing, New Delhi, pp. 347–354
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