SCIence in Architecture

Computer architecture research at Michigan Technological University — processors, compilers, and the boundary between them.

Five SCIA students and Prof. Soner Önder standing together in front of whiteboards covered in notes.
The SCIA group in Rekhi Hall, April 2026.

About the lab

SCIA /ˈskiː.ə/ — pronounced “skee-uh”; Latin for knowledge.

SCIA is the computer architecture research group of Prof. Soner Önder in the Department of Computer Science at Michigan Technological University.

We study how processors and compilers can work together to make programs run faster and more efficiently, with a particular focus on single-thread performance. Much of our work rethinks the boundary between hardware and software: executable single-assignment program representations, demand-driven execution of imperative programs, statically controlled multi-lane execution, and vectorization of the instruction space to turn hard-to-predict branches into data dependences.

We also build the infrastructure that makes this research possible — FAST, an architecture-description-language-driven simulator generator, and a shared in-house superscalar simulation framework that our students extend and use every day.

Our work is supported by the National Science Foundation and carried out in close collaboration with Prof. David Whalley's group at Florida State University and with the Computer Architecture Laboratory at NTNU in Trondheim, Norway, where our students have spent research summers through an NSF IRES program.

Most of us are Michigan Tech alumni ourselves. Students typically take on a piece of the shared infrastructure early and see it through to publication at venues such as ISCA, ICS, CGO, and LCTES; graduates have gone on to Apple, IBM, and faculty positions at Michigan Tech and Northern Michigan University.

Current projects Meet the group

News

  1. Can Fine-Grain Multi-threading Subsume VLIW? (Scott Pomerville, Soner Önder, Gang-Ryung Uh, David Whalley) is presented at LCTES 2026.
  2. Scott Pomerville (Ph.D. 2024) joins Northern Michigan University as an Assistant Professor of Computer Science. See our alumni.
  3. Sarah Larkin earns her M.S. in Computer Science on the way to the Ph.D.
  4. Scott Pomerville defends his dissertation, Statically Controlled Synchronized Lane Architectures, and receives the Midwestern Association of Graduate Schools Excellence in Teaching Award.
  5. Lab members spend the summer at NTNU's Computer Architecture Laboratory in Trondheim with FSU colleagues through the NSF IRES program; Facilitating the Bootstrapping of a New ISA is presented at LCTES 2023.
  6. NSF funds Vectorized Instruction Space (CCF-2211353), a collaborative project with Florida State University.

What we work on

Browse publications →

Microarchitecture

Fetch bandwidth, branch and memory-dependence prediction, misprediction recovery, and non-blocking memory hierarchies for high single-thread performance.

Compiler–architecture co-design

Executable single-assignment program representations (FGSA) that serve both the optimizing compiler and the machine's instruction set.

New execution paradigms

Demand-driven execution, statically controlled asynchronous lanes (SCALE), and vectorization of the instruction space (VIS).

Simulation infrastructure

FAST, an ADL-driven simulator generator with checkpointing, and a shared superscalar simulation framework used across our projects.